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[VHDL-FPGA-Verilog] SDRAM

Description: verilog编写的SDRAM实验，有串口调试助手和相关资料-Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!
Platform: | Size: 12167168 | Author: 网速卡 | Hits:

[Software Engineering] DDR3-SDRAM-controller

Description: My package named design DDR3 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory.
Platform: | Size: 6144 | Author: thuanbk | Hits:

[source in ebook] DDR3-SDRAM-Verilog-Model

Description: ddr3模型以及代码和测试程序，不过带有小瑕疵-ddr3 model and code and test procedures, but with small flaws
Platform: | Size: 61440 | Author: 陈国旗 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: verilog sdram读写控制，实现数据存储于发送-sdram read and write，data store and communication
Platform: | Size: 7168 | Author: john | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 用Verilog写的SDRAM测试程序。先向SDRAM里面写数据，然后再将数据读出来做比较。-Written using Verilog SDRAM test program. Xianxiang SDRAM write data inside, and then read out the data for comparison.
Platform: | Size: 8192 | Author: Daniel | Hits:

[VHDL-FPGA-Verilog] sdram_singale_word

Description: 使用verilog驱动的sdram单字节读写，可以学习一下sdram最基本的功能，学习sdram参考程序。-Use sdram verilog-driven single-byte read and write, you can learn the most basic functions sdram, sdram reference learning program.
Platform: | Size: 3072 | Author: | Hits:

[source in ebook] SDRAM_interface

Description: SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a refresh timer)
Platform: | Size: 2048 | Author: bryan | Hits:

[VHDL-FPGA-Verilog] sdram

Description: FPGA读写SDRAM。里面有详细的注释，供初学者参考，Verilog 语言-FPGA read SDRAM. There are detailed notes, reference for beginners,
Platform: | Size: 9007104 | Author: 果粒橙 | Hits:

[VHDL-FPGA-Verilog] SDRAM-controler-based-on-the-FPGA

Description: 本例是用FPGA器件实现SDRAM操作，所用语言为verilog硬件描述语言，希望可以对学习FPGA的人起到帮助作用-In this case is to achieve SDRAM operating with FPGA devices, and use of language verilog hardware description language, I hope people can learn to play FPGA helpful
Platform: | Size: 4372480 | Author: PrudentMe | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM-Controller

Description: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices
Platform: | Size: 262144 | Author: 马龙 | Hits:

[VHDL-FPGA-Verilog] 1-SDRAM

Description: 串行接口是最简单的一种通信方式，串口通信有两种方式，一种是同步串行，如SPI接口；另一种则是异步串行，即我们所说的UART。这个项目向大家展示了如何使用FPGA来模拟UART收发器。-uart fpga verilog
Platform: | Size: 13312 | Author: jackwu | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: sdram 状态机驱动源程序工程 完全使用verilog hdl写的-sdram state machine driver source project written entirely in verilog hdl
Platform: | Size: 4498432 | Author: 许明 | Hits:

[Driver Develop] S27_SDRAM_IP

Description: SDRAM 驱动读写demo，用verilog写的上板测试过-SDRAM verilog
Platform: | Size: 6847488 | Author: 夜星辰 | Hits:

[LabView] SDRAM-and-FIFO-for-DE1-SoC-master

Description: Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
Platform: | Size: 11482112 | Author: kimluan | Hits:

[VHDL-FPGA-Verilog] verilog-SDRAM

Description: 用verilog语言写的SDRAM读写控制器的程序，经测试有效。-Written in verilog language SDRAM read and write controller procedures, the test is valid.
Platform: | Size: 21216256 | Author: 谢嘉树 | Hits:

[VHDL-FPGA-Verilog] DDR3 SDRAM Verilog Model

Description: ddr3的逻辑带么参考，有需要的可以看一下。。。。。。。。。(ddr3 ssscoede code code code)
Platform: | Size: 70656 | Author: sss911 | Hits:

[VHDL-FPGA-Verilog] 4NandFlash

Description: 控制器顶层，以及实现功能模块简单的snandflash_top_ctrler(Simple nand_flash_top_ctrler)
Platform: | Size: 2048 | Author: 哒嘟嘟 | Hits:

[VHDL-FPGA-Verilog] sdram_verilog

Description: verilog实现外部sdram读写功能，实测可用(SDRAM read and write function by verilog)
Platform: | Size: 659456 | Author: fgghz | Hits:

[VHDL-FPGA-Verilog] sdram_ip

Description: 完成SDRAM的上电配置，状态机编写其读写模块，存储模块，并通过两个异步作为存储和读取的通道(Complete the SDRAM power-on configuration, the state machine to write its read-write module, memory module, and through two asynchronous as a storage and read the channel)
Platform: | Size: 166912 | Author: 子炎恋紫雪 | Hits:

[VHDL-FPGA-Verilog] my_sdram_mdl

Description: 此功能为altera fpga 的sdram 控制器，串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
Platform: | Size: 1206272 | Author: flyhouse112 | Hits:
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